1. Field of the Invention
Exemplary aspects of the present invention generally relate to image processing devices such as a digital printer, a scanner, a facsimile machine, and a digital multifunction printer having two or more of copying, printing, scanning, and facsimile functions, an image processing method employed in the image processing device, and a recording medium storing an image processing program.
2. Description of the Background
In order to satisfy demand for lower energy consumption, lower production cost, downsizing of devices, and so forth, image processing devices now generally employ application specific integrated circuits (ASICs) for input/output (I/O) control system such as universal serial bus (USB) and media access control (MAC). ASICs make it possible to control interrupt signals from a central processing unit (CPU), for example, and enable changes to be made to the wiring between elements on a chip.
Generally, the operating mode of the image processing device can be switched between a normal operating mode, in which image processing is performed, and an energy-saving mode, in which energy consumption is reduced as compared to the normal operating mode. In such an image processing device, multiple CPUs for handling interrupts depending on the operating mode may be included in the ASIC.
When receiving interrupt signals from multiple CPUs, the ASIC selects an interrupt signal sent from one of the CPUs to handle the interrupt signal thus selected. Consequently, interrupt factors in the other CPUs are deleted while the ASIC handles the interrupt signal thus selected, causing a system error and halt of the image processing device.
To solve such problems, Published Unexamined Japanese Patent Application No. (hereinafter referred to as JP-A-) H10-011411 discloses a multiprocessor system in which destinations to notify multiple interrupt generation factors are not fixed, but are instead dynamically changeable.
Another approach is disclosed in JP-A-H09-081402, in which a processor to receive an interrupt from a data transfer processing device can be changed by software, such that a multiprocessor system including an interrupt destination control means with a higher degree of freedom can be achieved.
Yet another approach is disclosed in JP-A-2001-125880, in which, in a multiprocessor system, an interrupt from a particular processor is handled first according to a priority level of interrupts sent from an I/O control system.
However, in the above-described multiprocessor systems of the related-art, when an interrupt is received at the same time the operating mode of the image processing device is switched, a large lag arises between a time when the interrupt is generated and a time when the interrupt is reported. Consequently, the interrupt cannot be properly handled.
Specifically, in a case in which CPUs for handling interrupts are switched depending on the operating mode of the image processing device, an interrupt control wire on a peripheral component interconnect (PCI) bus is used in one of the CPUs whereas a local interrupt control wire is used in the other CPU. Consequently, a difference in communication speed between the CPUs causes the large difference between the time of generation of the interrupt and the time of notification of the interrupt. As a result, the interrupt is not properly handled.
Further, because the CPUs are turned on and off via a chip set in the related-art image processing device, in a case in which the operating mode of the image processing device is changed to the normal operating mode using a weekly timer or the like in the chip set, the image processing device enters a Suspend-to-RAM mode, in which data in the CPUs is temporarily saved in a memory, again after the CPUs are turned on.